1. Field of the Invention
The present invention is related to a pixel driving circuit, and more particularly, to a pixel driving circuit in which a number of digital-to-analog converters required by a data driving circuit can be reduced.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a pixel driving circuit 100 of the prior art for reducing color washout. The pixel driving circuit 100 comprises a plurality of pixels, data lines DL1-DLM, scan lines SL1-SLN, a data driving circuit 110 and a scan driving circuit 120. Pixels PIX1 and PIX2 are utilized to exemplify structures of the plurality of pixels. The pixel PIX1 comprises transistors Q1 and Q2, a main region MR1 and a sub region SR1. The transistor Q1 comprises a first electrode 1, a second electrode 2 and a gate end G. The first electrode 1 of the transistor Q1 is coupled to the data line DLX, the second electrode 2 of the transistor Q1 is coupled to the main region MR1, and the gate end G of the transistor Q1 is coupled to a scan line SLY. The transistor Q2 comprises a first electrode 1, a second electrode 2 and a gate end G. The first electrode 1 of the transistor Q2 is coupled to the data line DL(X+1), the second electrode 2 of the transistor Q2 is coupled to the sub region SR1, and the gate end G of the transistor Q2 is coupled to the scan line SLY. The pixel PIX2 comprises transistors Q3 and Q4, a main region MR2 and a sub region SR2. The transistor Q3 comprises a first electrode 1, a second electrode 2 and a gate end G. The first electrode 1 of the transistor Q3 is coupled to the data line DL(X+2), the second electrode 2 of the transistor Q3 is coupled to the sub region SR2, and the gate end G of the transistor Q3 is coupled to the scan line SLY. The transistor Q4 comprises a first electrode 1, a second electrode 2 and a gate end G. The first electrode 1 of the transistor Q4 is coupled to the data line DL(X+3), the second electrode 2 of the transistor Q4 is coupled to the main region MR2, and the gate end G of the transistor Q2 is coupled to the scan line SLY.
When a scan driving circuit 120 drives the scan line SLY, transistors Q1-Q4 are turned on, for the main region MR1 to couple to the data line DLX via the transistor Q1, the sub region SR1 to couple to the data line DL(X+1) via the transistor Q2, the sub region SR2 to couple to the data line DL(X+2) via the transistor Q3, and the main region MR2 to couple to the data line DL(X+3) via the transistor Q4.
Assume the pixel PIX1 is to display frames corresponding to digital data DA1, and the pixel PIX2 is to display frames corresponding to digital data DA2. For the pixel PIX1, the main region MR1 and the sub region SR1 receive and store gray level voltages corresponding to the digital data DA1 from the data driving circuit 110 via data lines DX and D(X+1) respectively. For the pixel PIX2, the main region MR2 and the sub region SR2 receive and store gray level voltages corresponding to the digital data DA2 from the data driving circuit 110 via data lines D(X+3) and D(X+2) respectively. Further, a voltage level of the gray level voltage stored in the main region MR1 corresponds to a voltage level of the gray level voltage stored in the sub region SR1, and a voltage level of the gray level voltage stored in the main region MR2 also corresponds to a voltage level of the gray level voltage stored in the sub region SR2, so as to reduce color offset when viewing the pixel driving circuit 100 from different viewing angles.
However, since in the pixel driving circuit 100, the gray level voltage stored in the main region MR1 is different from that of the sub region SR1, the gray level voltage stored in the main region MR2 is different from that of the sub region SR2, and a rotating polarity for each region (MR1, MR2, SR1, SR2) can be positive or negative, the data driving circuit 110 requires a corresponding digital-to-analog converter and a corresponding negative digital-to-analog converter for each of the data lines DLX-DL(X+3), for providing positive and negative gray level voltages to the main regions MR1 and MR2 and sub regions SR1 and SR2. In other words, when the pixel driving circuit 100 comprises M data lines, the data driving circuit 110 requires 2*M digital-to-analog converters. Since digital-to-analog converters occupy substantial circuit area, the cost of the data driving circuit 110 and the power consumption of the pixel driving circuit 100 are significantly increased, causing inconvenience to the user.